10T SRAM Circuitry Clocks at 3.1 GHz

Xu Jianming and Peng Xuhong, Shaoyang University

By taking advantage of the fine dimensions and fast operating speeds of a 65-nm silicon CMOS process technology, this 10T SRAM design significantly improves static noise margin versus 8T SRAM.

By taking advantage of the fine dimensions and fast operating speeds of a 65-nm silicon CMOS process technology, this 10T SRAM design significantly improves static noise margin versus 8T SRAM.

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from Electronic Design http://ift.tt/1HWj73N